In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers (e.g., at submicron levels). In order to accomplish such high device packing density, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist and an exposing source (such as optical light, x-rays, etc.) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The ability to reduce the size of computer chips while increasing packing densities and performance is driven by lithography technology and metallization processes and is especially critical to ultra large scale integration (ULSI) circuits. ULSI circuits require responsive changes in interconnection technology which is considered a very demanding aspect of ULSI technology. High density demands for ULSI integration require planarizing layers with minimal spacing between conductive lines and/or trenches.
Traditional methods of forming interconnection structures include the use of photoresist patterning and chemical or plasma subtractive etching as the primary metal technique. However, because the geometry of semiconductor circuits continues to decrease, traditional interconnection techniques are unsuitable. In particular, problems associated with traditional methods include trapping impurities or volatile materials, such as aluminum chloride, in interwiring spaces (i.e., may pose reliability risk to device), leaving residual metal stringers (i.e., may cause electrical shorts) and poor step coverage. These problems contribute to low yields, poor performance, and lower layout densities. More recent developments in interconnect technology have improved, however, problems such as non-uniform seed layer deposition and void formation within the seed layer still contribute to poor device performance and product yield losses. The seed layer is commonly deposited or formed over a barrier layer for the purpose of providing a material on which a subsequently deposited material will readily form. Therefore, seed layer coverage is critical to the formation and performance of the interconnect structure.
Therefore, there is an unmet need for a process to determine the sufficiency of seed layer coverage in the sidewall portions of a trench.